1. Field of Invention
The present invention relates to a method of manufacturing a dual damascene. More particularly, the present invention relates to a method of manufacturing a dual damascene by using low dielectric constant (K) material.
2. Background
FIGS. 1A through 1E are cross-sectional views showing the progression of conventional manufacturing steps in producing a dual damascene.
As shown in FIG. 1A, a substrate structure 100 is provided. For clarity, devices within the substrate structure 100 are not sketched. A defined conductive layer 102 is formed in the substrate structure 100. An oxide layer 104 and a silicon nitride layer 106 aresubsequently formed over the substrate 100 and the conductive layer 102.
As shown in FIG. 1B, the silicon nitride layer 106 is defined by a photolithography method to form an opening exposing the oxide layer 104. Then, an insulation layer 108 is formed over the defined silicon nitride layer 106a and the oxide layer 104 exposed within the opening.
As shown in FIG. 1C, a photoresist pattern (not shown) is used to define the insulation layer 108 by, for example, an anisotropic dry etching method. Using the silicon nitride layer 106a as an etching mask, the oxide layer 104 within the opening is etched away until the conductive layer 102 and the silicon nitride layer 106a are exposed so that trenches 110a and 110b are formed. Trench 110a is formed in the insulation layer 108 (FIG. 1B), silicon nitride layer 106a and oxide layer 104, and exposes the conductive layer 102. Trench 110b is formed in the insulation layer 108 and exposes the silicon nitride layer 106a. The remaining portions of insulation layer 108 are referred to as 108a, 108b and 108c.
As shown in FIG. 1D, a barrier layer 112 is formed over the surface of the trenches 110a and 110b. A metal layer 114 is then formed over the barrier layer 112 and fills the trenches 110a and 110b.
As shown in FIG. 1E, using a chemical mechanical polishing (CMP) method, the redundant portions of metal layer 114 and barrier layer 112 above the insulation layers 108a, 108b and 108c are removed to form via 114a and conductive lines 114b and 114c.
As the size of semiconductor devices is reduced to 0.25 .mu.m, the distance between the conductive line 114b and the conductive line 114c is reduced. Therefore, a capacitor effect will take place on the insulation layer 108b located between the conductive lines 114b and 114c. An additional current is caused by the capacitor effect, hence interfering with the normal operations of the conductive lines 114b and 114c. RC delay and the reduction of the performance of the devices are also caused by the capacitor effect.
Moreover, the decreasing step coverage of the barrier layer 112 accompanies the reduction in width of the trench 110a. Therefore, protruding shapes are formed on the barrier layer 112 at the corners of the trenches 110a and 110b. These protruding shapes obstruct the deposition of the metal layer 114.